Typically, a video processing solution is composed of hardware accelerators (HWAs), connected to a central programmable unit (CPU) that is in charge of initializing and starting the different hardware accelerators along with managing all their input/output data transfers. As the image resolutions to be processed become higher and video standards become more complex, the number of hardware accelerators needed to support such features may increase. Thus the task scheduling on the different HWAs may become a bottleneck that requires increased processing capabilities in the CPU. Increasing performance of the CPU may be detrimental to size and power usage.
In a typical implementation of a centralized system, all nodes are activated and controlled by the central CPU. Data can be exchanged between nodes and the CPU either by a common memory or by DMA (direct memory access). The CPU typically responds to interrupt requests from the various HWAs to schedule tasks. In a centralized implementation, the synchronization time for a given HWA usually depends on the processor interrupt latency and the explicit or implicit priority assigned to this HWA. When each HWA is connected to a distinct interrupt line with an associated priority, explicit priority exist, and when the interrupt line is shared, the order of processing interrupts will create implicit priority. Thus, the synchronization time is hard to predict.